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Extra resources for Introduction to CPLD and FPGA Design

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DFT techniques should be taken into account during the design process rather than afterwards. Otherwise, circuits can be designed that are later found to be difficult, if not impossible, to test. One important consideration that can be overlooked, is that test logic is intended to increase the testability and reliability of your chip. If test logic becomes too large, it can actually decrease reliability because the test logic can itself have problems which cause the chip to malfunction. A rule of thumb is that test circuitry should not make up more than 10% of the logic of the entire chip.

Test signals can be used to select which output is being observed. If no pins are available, the state bits can be muxed onto an existing pin which, during testing, is used to observe the state machine. This allows for much easier debugging of internal state machines. 4 Scan Techniques Scan techniques, shown in Figure 35, allow the nodes of the chip to be scanned out so that they can be observed externally. There are two main scan techniques - full scan and boundary scan. Full scan is extremely flexible, especially since it can also allow values to be scanned into the chip so that you can start it from a known state.

This is particularly useful if a problem occurs only after the chip has been operating for a long time. A state can be quickly scanned into the chip which corresponds to the state which would normally be reached after a long time in operation. The drawback of scan techniques are that they require a lot of software development to support. Also, if states are scanned into the chip, you must be careful not to scan in illegal states. It is possible to turn on multiple drivers to a single net internally which would normally not happen, but which would burn out the chip.

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